1. Field of the Invention
This invention relates to the field of integrated circuits including cache memories. More particularly, this invention relates to how to deal with such integrated circuits having cache memories which have a variable size.
2. Description of the Prior Art
It is known to provide integrated circuits, such as microprocessors, with cache memories for locally storing one or more of instructions and data. The cache memory gives high speed access to the stored information. Depending upon the particular use of an integrated circuit, the requirements for the size of the cache memory can vary considerably. Providing too little cache memory can have a significant performance degrading effect, whereas providing too much cache memory needlessly increases the cost, power consumption, size etc of the integrated circuit. For these reasons it is known to provide integrated circuit designs where a manufacturer of that design can select a particular size of the cache memory to be provided depending upon the use intended for an integrated circuit.
One way of providing for such variable cache size is to include within the design, and in particular within the cache controller design, user defined parameters which specify the cache size to be provided. When that design (such as RTL code) is compiled, the appropriate controller for the cache size specified is generated. This approach suffers from the disadvantage that all possible combinations of the user defined cache size parameters require validation and this significantly increases the required validation effort and associated cost. The cache RAM integration tests should also be parameterized by the same user defined parameters and validated for all options. Finally, this approach does not make it possible to harden the core design (i.e. fix a particular compiled design that is known to be satisfactory and reuse this in other circumstances) since it will not be suited for use with different cache sizes.
Another possible approach is to provide the cache controller with suitable logic, such as masking logic, which can be configured with static configuration pins to select a particular cache size which has been implemented. One disadvantage with this approach is that the masking logic is redundant for a chosen cache size and yet needs to be provided to give the flexibility within the design. Thus, the redundant logic represents a disadvantageous overhead. In addition, the masking logic used is usually located in timing critical paths where it introduces a disadvantageous path delay. Furthermore, integration testing needs to be performed with a knowledge of the configuration pin values being used and this increases the complexity of the integration testing.